Top Design Engineer Jobs in Bengaluru

Lead all block/chip level physical design activities, including floor planning, RC extraction, PNR, STA, and verification for GPUs and ASICs. Collaborate with design teams to troubleshoot issues and improve RTL2GDS flow for enhanced performance. Utilize strong knowledge in implementation methodologies and scripting for tool automation.

The Senior SoC Design Engineer will be responsible for driving SoC execution, collaborating with multi-functional teams, and ensuring comprehensive SoC design. The role involves quality checks, bug triaging, and mentoring junior engineers. Strong knowledge of SoC architecture and peripherals is essential.

Seeking passionate and creative senior design engineers to work on state-of-the-art memory subsystem components for Graphics Processors. Responsibilities include micro-architecture design, RTL development, verification, collaboration with teams, and post-silicon verification. Must have 4+ years of design experience and expertise in Verilog.

The Senior CPU Design Engineer will design and implement complex CPU modules, make architectural trade-offs, develop micro-architectures in RTL, and support silicon validation. The role includes collaboration with various engineering teams to ensure successful project execution.

The Layout Design Engineer will be responsible for executing IC layouts for high-speed digital and analog circuits using advanced CMOS process nodes. This role involves delivering layouts for specialized circuit solutions and adopting best layout practices while adhering to company procedures.

Design and implement hardware for SoCs and GPUs, focusing on micro-architecture and RTL development. Collaborate with various teams for verification, power, and timing requirements, ensuring design compatibility. Engage in post-silicon verification and debugging tasks.

The ASIC Design Engineer is tasked with developing and enhancing timing analysis/signoff workflows, managing chip level integration, physically partitioning and floor planning, and optimizing designs. This role includes creating custom timing scripts for clock skew analysis and engaging in design optimization tasks to ensure effective design implementation from micro-architecture to tape-out.

Design and implement SoCs, defining micro-architectures and developing RTL while collaborating with verification teams. Responsibilities include owning silicon bring-up, mentoring junior engineers, and ensuring accurate verification and implementation of features.

As a Circuit Design Engineer at NVIDIA, you will work on designing circuit IPs, improving performance parameters, and mentoring junior engineers. You'll leverage your knowledge of CMOS and circuit methodologies to propose innovative solutions and collaborate with global teams on memory design challenges.

The Senior Principal Design Engineer at Cadence is responsible for developing software for embedded processors and emulation platforms, focusing on efficient algorithms and data structures. The role demands strong programming skills in C/C++ and experience in firmware programming. Additionally, the engineer will collaborate with teams and customers while potentially engaging in international travel. A solid foundation in computer architecture and understanding of Neural Networks is beneficial.

The Principal Design Engineer will lead design verification projects, ensuring complex designs are verified from concept to closure. Key responsibilities include environment planning, test plan generation, and developing functional verification environments using System Verilog and UVM.

As a Principal Design Engineer, you will be responsible for the verification of Serial and Interface Design IPs, utilizing UVM testbench development for efficient verification and participating in formal verification and emulation qualification. The role requires strong analytical, problem-solving skills, and effective communication capabilities.

As a Lead Design Engineer at Cadence, you will work on embedded processors, implement high-performance algorithms, and write/debug software for emulation platforms. You'll collaborate with diverse teams and customers to address issues while leveraging knowledge in Neural Networks and Deep Learning.

The Principal Design Engineer will lead major blocks of Memory PHY layout design, engaging in hands-on critical analog and high-speed layout blocks. Responsibilities include coordinating with circuit leads, layout contractors, and team members, as well as participating in layout reviews.

The Lead Design Engineer at Cadence will develop firmware for various memory interfaces, collaborate with hardware designers and architects, deduce co-verification plans with the verification team, and support debugging efforts on simulations and silicon boards.

The Principal Design Engineer at Cadence is responsible for leading design verification projects, confirming complex designs are verified from concept to closure. This role requires extensive experience in functional verification fundamentals, test plan generation, and environment development using System Verilog and UVM.

The Principal Design Engineer is responsible for the integration, customization, and post-silicon bring-up of CDNS DDR IP subsystems. This role involves resolving complex implementation issues, supporting integration reviews, performing simulations for functionality, and enhancing customer communication and experience.