Top Design Engineer Jobs in Bengaluru

Lead RTL micro-architecture and implementation of ultra-low-power communication SoC blocks. Perform RTL linting, simulation, CDC/DRC checks, gate-level simulations, MBIST/DFT integration, ECOs, and power-aware verification using UPF and VCS-NLP. Collaborate with architects, analog teams, and handle timing closure and hardmacro integration.

Design and lead development of miniaturized PCBs for wearable devices using custom Wi-R ICs and COTS components. Create schematics and layouts, perform board-level testing and debugging, collaborate on packaging, and support prototype validation and test automation.

Design, analyze, and tape-out low-power mixed-signal and RF circuits for wearable communication chips. Integrate analog IP into SoCs, verify and validate designs, collaborate with firmware/board/testing teams, and perform lab validation from schematic through layout and tape-out.

Design and develop mechanical components and enclosures using CAD. Create 3D models, assemblies, and manufacturing drawings. Support prototyping, vendor coordination, tolerance analysis, material selection, manufacturability, field testing, and documentation while collaborating with electronics and hardware teams.

Own physical implementation and sign-off of advanced semiconductor blocks from RTL through GDSII. Responsibilities include synthesis, floorplanning, placement, CTS, routing, timing closure, extraction, physical verification, EM/IR analysis, and PPA optimization. The role develops automation and methodology flows, resolves complex design-closure issues, collaborates across architecture and silicon teams, leads tapeout execution, and mentors engineers working on AI, CPU, GPU, memory, and other high-performance designs.

Develop and maintain mission design software for space situational awareness infrastructure. Responsibilities include orbital and mission simulations, computational optimization, sensitivity analysis, delta-V and link budgets, mission operations planning, sensor scheduling, software deployment, testing, technical reviews, and stakeholder presentations.

Lead microarchitecture and RTL development for complex connectivity IPs and subsystems. Translate system requirements into high-performance hardware designs, optimize latency, area, and power, and address flow control, buffering, arbitration, and error handling. Collaborate with verification, SoC integration, and physical design teams; support silicon bring-up and post-silicon debugging. Provide technical leadership through reviews, architecture ownership, and mentoring.

Own functional verification of custom CPU units from test planning through coverage closure. Build SystemVerilog and UVM environments with C/C++, stimulus, checkers, assertions, trackers, and coverage. Verify instruction execution, caches, memory ordering, coherence, exceptions, privilege behavior, and performance. Execute regressions, support emulation and FPGA prototyping, enable pre-silicon software bring-up, and debug hardware-software issues across multidisciplinary teams.

Develop and execute verification strategies for complex SoC hardware, including compute engines, memory systems, interconnects, processors, DMA, and system software interactions. Build SystemVerilog and UVM environments, assertions, checkers, scoreboards, and formal verification workflows. Analyze performance, latency, bandwidth, QoS, and real-time behavior; support emulation, FPGA prototyping, pre-silicon bring-up, post-silicon debugging, and hardware-software root-cause analysis.

Develop and execute verification strategies for complex Physical AI SoC components and full HW/SW systems. Build SystemVerilog and UVM environments, assertions, checkers, scoreboards, and formal verification flows. Verify processors, memory, interconnects, DMA engines, and accelerators for correctness, performance, safety, and reliability. Lead emulation, FPGA prototyping, pre-silicon validation, post-silicon debugging, root-cause analysis, and system-level workload testing while collaborating across architecture, RTL, software, and systems teams.

Own verification of custom AI accelerator hardware, including matrix and vector compute engines. Develop SystemVerilog and UVM environments, reference models, assertions, checkers, coverage, and regression infrastructure. Verify numerical precision, quantization, data flow, performance, and reliability across RTL blocks and subsystems. Collaborate with architecture, RTL, software, compiler, and runtime teams through emulation and silicon bring-up.

Lead RF/analog/mixed-signal chip tapeouts from design through validation, integrate analog IPs into SoCs, prototype high-speed systems, mentor the team, validate silicon with test automation, and contribute to PCB design and firmware bring-up for wearable devices.

Perform RTL integration of IPs and subsystems into top-level SoCs, develop RTL wrappers, interconnect, clock/reset infrastructures; run lint/CDC/early synthesis checks; debug simulation and synthesis issues; automate and maintain integration flows with Python/Perl/Tcl; collaborate with design, verification, and physical design teams and contribute to design reviews and documentation.

Creates detailed 2D drawings and 3D CAD models, collaborates with engineers and architects, manages technical documentation and drawing databases, supports design reviews, and identifies innovative solutions. The role requires adaptability, assertive communication, attention to detail, teamwork, and willingness to handle varied responsibilities in a fast-paced startup environment.

Design and develop Class I and II medical devices from concept through commercialization. Responsibilities include CAD modeling, manufacturing drawings, DFMEA, risk assessment, DFM/DFA, prototyping, verification and validation testing, BOMs, engineering documentation, ECN/ECR management, quality issue resolution, and manufacturing support. The role collaborates with industrial design, electronics, manufacturing, quality, and regulatory teams while ensuring compliance with medical device standards.

Develop and maintain production-ready electrical schematics, PCB layouts, drawing templates, component libraries, BOMs, and approved alternate parts lists. Review designs for integrity, manufacturability, testability, and documentation completeness. Coordinate with procurement, manufacturing, quality, and engineering teams to resolve component and production issues while maintaining engineering changes, revisions, and accurate product records.

Lead architecture and RTL development for UALink IP and subsystems. Translate protocol requirements into scalable hardware architectures, design high-bandwidth low-latency datapaths and control logic, and optimize performance, power, area, and latency. Develop and review SystemVerilog RTL, collaborate with verification, physical design, integration, and firmware teams, debug complex issues, contribute to architecture decisions, and mentor engineers.

Lead the architecture, microarchitecture, RTL design, integration, and silicon bring-up of complex connectivity IP and subsystems. Develop high-performance logic using SystemVerilog/Verilog, addressing flow control, ordering, buffering, arbitration, error handling, and reliability. Optimize performance, latency, area, and power; collaborate with verification, SoC integration, and physical design teams; debug post-silicon issues; lead technical reviews and mentor engineers.

Design, analyze, optimize, and validate precision optical systems for Earth observation satellite payloads. Responsibilities include optical requirements definition, Zemax modeling, tolerancing, stray-light mitigation, manufacturing and opto-mechanical integration support, testing, documentation, and vendor coordination. The role supports designs from concept through manufacturing, integration, and verification while balancing technical, schedule, and budget constraints.

Lead the end-to-end development of Earth observation imaging payloads, including payload architecture, optical and opto-mechanical design, requirements, integration, verification, testing, image quality analysis, launch preparation, and in-orbit calibration. Coordinate subcontractors, collaborate with satellite platform teams, manage performance budgets, and drive feasibility studies and future optical payload technology programs.

Leads RTL and microarchitecture development for UALink IP and subsystems, designing high-performance control and data-path logic for scalable, low-latency interconnects. Responsibilities include buffering, arbitration, flow control, ordering, error handling, optimization, SystemVerilog development, debugging, silicon support, cross-functional collaboration, RTL review, and mentoring engineers.

Lead end-to-end antenna and phased-array architecture for a spaceborne SAR payload, including electromagnetic design, simulation, analytical validation, beamforming coordination, RF-thermal-mechanical analysis, measurement, environmental qualification, integration, and in-orbit support. The role requires deep antenna theory, phased-array expertise, antenna testing experience, technical documentation skills, and cross-functional collaboration. The engineer will also mentor junior staff and support flight qualification.

Lead mechanical design for consumer electromechanical products from concept through production. Responsibilities include CAD modeling, prototyping, testing, thermal/fluid/structural analysis, cross-functional collaboration, DFM/DFA, tolerance analysis, and manufacturing ramp support in Asia. The role requires designing plastic, metal, and soft goods components integrated with sensors and actuators, supporting high-volume manufacturing, and traveling to China as needed.

Leads the mechanical design, analysis, optimization, manufacturing support, commissioning, and continuous improvement of high-pressure, high-temperature tubular and plug flow reactors. Responsibilities include pressure vessel design, FEA and stress analysis, materials selection, mechanical integrity assessments, vendor and fabrication support, code compliance, troubleshooting, root cause analysis, technical reviews, mentoring engineers, and client discussions across chemical and process industries.

Leads end-to-end hardware architecture and development for high-reliability airborne and space electronics. Responsibilities include component selection, power architecture, schematic and PCB design, embedded processor and peripheral integration, vendor coordination, hardware bring-up, debugging, testing, compliance, and technical documentation. The role requires expertise in power supplies, high-speed interfaces, RF circuits, signal and power integrity, EMI/EMC-compliant layouts, and collaboration with firmware and cross-functional teams.