Top Design Engineer Jobs in Bengaluru

Join a startup as a Physical Design Engineer, focusing on RTL-to-GDSII implementation, performance optimization, and AI-driven automation.

The Hardware Design Engineer will design, develop, and test electronics circuits and systems, collaborating with teams for enhanced product performance.

Lead RTL Design Engineer for wireless baseband architecture, overseeing design teams, implementing RTL designs, and ensuring adherence to methodologies.

Design and implement RTL blocks for wireless systems, perform synthesis on FPGAs, and collaborate with software and hardware teams.

The Hardware Design Engineer will design and develop digital and analog electronics, oversee control boards, and collaborate cross-functionally.

The role involves leading a team of Physical Design engineers in delivering high-performance silicon products while ensuring adherence to timing, power, and area requirements. Responsibilities include technical leadership, hands-on ownership of critical blocks, automation development, and stakeholder management to meet project milestones.

Design high-performance analog-to-digital and digital-to-analog converters, including circuits from specification to market introduction, while evaluating silicon and utilizing lab equipment.

The role involves high-performance analog and mixed-signal IC design, from specification to product introduction, requiring extensive experience in circuit design and lab evaluation.

Design and verify digital controllers for high-performance data converters, including coding in Verilog, behavioral modeling, and customer support.

Design and develop mechanical systems for aerospace applications, focusing on ruggedness and lightweight mechanisms, while collaborating with diverse teams.

The Lead RF Hardware Design Engineer will lead the design and development of RF hardware for satellite communication systems, guiding a team through complex design challenges.

The Junior Mechanical Design Engineer will support the design and development of mechanical subsystems, create 3D CAD models, contribute to structural analysis, and assist in prototyping and testing.

Design and optimize custom digital logic for UAVs focusing on motion control, neural network acceleration, and real-time computation. Responsibilities include RTL architecture design, collaboration with engineers, integration of custom RTL blocks, and optimization for performance and reliability.

The Microarchitect and RTL Design Engineer will design microarchitectures, ensure optimal performance in RTL coding, and collaborate with software and verification teams to meet project requirements.

Seeking a Physical Design Engineer to manage RTL to GDS flows, collaborate on performance trade-offs, and develop physical design methodologies.

The role involves designing and integrating SoC/IP, performing RTL quality checks, managing subsystem issues, supporting verification teams, and creating design documents.

The ASIC Design Engineer will develop SoCs, micro-architecture design, RTL coding, optimization, and collaborate with multiple teams for ASIC development.

Design high-performance analog-to-digital and digital-to-analog converters, evaluate silicon, and oversee layout in advanced CMOS processes.

Design and verify digital datapaths for high-performance ADCs and DACs using RTL, assist with synthesis and timing closure, and automation through scripting.

The Senior Analog IC Design Engineer will work on high-speed analog designs, collaborate with teams for implementation, and analyze performance tradeoffs.

Design and verify high-performance digital and mixed-signal ICs, focusing on RTL design, behavioral modeling, and digital control circuits.

The Senior Digital Design Engineer will design, verify, and validate digital architecture for automotive and space applications, focusing on RTL and FPGA.

Lead block-level physical implementation from synthesis and floorplan through CTS, routing, and sign-off. Optimize PPA via deep timing, power, and congestion analysis, automate flows with Tcl/Python, resolve DRC/LVS/IR/timing issues, and collaborate with RTL/DFT teams to left-shift constraints and ensure clean GDSII tape-outs.

Lead full RTL-to-GDSII physical design for sub-5nm SoCs: own full flow, optimize PPA, build scalable push-button methodology, remove execution bottlenecks, and collaborate with RTL/Architecture/DFT/foundry/EDA teams.

Lead SoC physical design including P&R, floorplanning, clocking, timing and power closure. Develop methodologies, run signoff flows (timing, power, EM/IR, PDV), collaborate with micro-architects for PPA tradeoffs, and drive tape-out readiness for deep-submicron (7nm or below) designs.