Top Design Engineer Jobs in Bengaluru

The Senior Analog IC Design Engineer will implement SerDes, PLL, ADC/DAC, and PMU modules, working closely with architecture and layout teams to ensure verification and optimization of designs.

Lead RTL and FPGA design and verification for digital architecture at Omni Design, ensuring implementation and validation of semiconductor solutions.

The Senior Product Design Engineer is responsible for mechanical design, fixture design, testing, and maintenance of products, collaborating with suppliers, and improving product performance.

The Senior Antenna Design Engineer will lead the development of high-frequency antennas for satellite communication, performing electromagnetic simulations, prototyping, testing, and ensuring compliance with aerospace standards. They will collaborate with RF and system engineers to integrate antennas while optimizing designs for performance in extreme environments.

The Senior Digital Design Engineer will design and implement high-performance digital solutions with a focus on RTL development and timing closure. Responsibilities include IP integration, overseeing design processes from architecture to GDS, and performing pre- and post-silicon debug.

The Structural Design Engineer will be responsible for designing light gauge steel and HRS framing, preparing structural design reports, reviewing engineering drawings for quality assurance, and providing design recommendations to enhance business opportunities. The role involves research and development for new construction methodologies and collaboration with other engineers for design development.

The Principal Digital Design Engineer will design and implement high-performance digital solutions, focusing on RTL development, micro-architecture, and IP integration for processor and peripherals. Responsibilities include ensuring timing closure, overseeing design verification, and collaborating with cross-functional teams.

The Senior Digital Design Engineer will develop high-performance digital solutions, focusing on RTL development and synthesis. Responsibilities include collaborating on IP integration for PCIe/CXL, ensuring timing closure, and utilizing Synopsys/Cadence tools for verification. The role emphasizes practical experience in high-speed protocol design and post-silicon debugging.