Top Design Engineer Jobs in Bengaluru

Hands-on RF/mixed-signal engineer to design, implement, bring-up and test wireless communication hardware (PCB-level IC integration). Work with high-speed RF DACs/ADCs, ADS/HFSS, JESD204B; phased array, Ku-band and mmWave experience desirable.

Design, simulate, and validate antenna systems for space and terrestrial applications using HFSS/CST. Perform FEM/FDTD simulations, impedance matching, prototyping with PCB teams, and hands-on VNA/anechoic chamber testing.

Design high-performance analog-to-digital and digital-to-analog converters, evaluate silicon, and oversee layout in advanced CMOS processes.

Design and verify digital datapaths for high-performance ADCs and DACs using RTL, assist with synthesis and timing closure, and automation through scripting.

The Senior Analog IC Design Engineer will work on high-speed analog designs, collaborate with teams for implementation, and analyze performance tradeoffs.

Design and verify high-performance digital and mixed-signal ICs, focusing on RTL design, behavioral modeling, and digital control circuits.

The Senior Digital Design Engineer will design, verify, and validate digital architecture for automotive and space applications, focusing on RTL and FPGA.

Lead block-level physical implementation from synthesis and floorplan through CTS, routing, and sign-off. Optimize PPA via deep timing, power, and congestion analysis, automate flows with Tcl/Python, resolve DRC/LVS/IR/timing issues, and collaborate with RTL/DFT teams to left-shift constraints and ensure clean GDSII tape-outs.

Lead full RTL-to-GDSII physical design for sub-5nm SoCs: own full flow, optimize PPA, build scalable push-button methodology, remove execution bottlenecks, and collaborate with RTL/Architecture/DFT/foundry/EDA teams.

Lead SoC physical design including P&R, floorplanning, clocking, timing and power closure. Develop methodologies, run signoff flows (timing, power, EM/IR, PDV), collaborate with micro-architects for PPA tradeoffs, and drive tape-out readiness for deep-submicron (7nm or below) designs.

Design and develop mechanical systems for enclosure structures and payload integration; perform FEA and simulations; produce CAD models, assemblies, and specifications; oversee fabrication, assembly, and testing; conduct design reviews and ensure compliance with space environmental standards.

Join a startup as a Physical Design Engineer, focusing on RTL-to-GDSII implementation, performance optimization, and AI-driven automation.

The Hardware Design Engineer will design, develop, and test electronics circuits and systems, collaborating with teams for enhanced product performance.

Lead RTL Design Engineer for wireless baseband architecture, overseeing design teams, implementing RTL designs, and ensuring adherence to methodologies.

Design and implement RTL blocks for wireless systems, perform synthesis on FPGAs, and collaborate with software and hardware teams.

Design high-performance analog-to-digital and digital-to-analog converters, including circuits from specification to market introduction, while evaluating silicon and utilizing lab equipment.

The role involves high-performance analog and mixed-signal IC design, from specification to product introduction, requiring extensive experience in circuit design and lab evaluation.

Design and verify digital controllers for high-performance data converters, including coding in Verilog, behavioral modeling, and customer support.

Seeking a Principal Physical Design Engineer with extensive experience in SoC/product development, physical design tools, and ownership from architecture to GDSII.

The Microarchitect and RTL Design Engineer will design microarchitectures, ensure optimal performance in RTL coding, and collaborate with software and verification teams to meet project requirements.

Seeking a Physical Design Engineer to manage RTL to GDS flows, collaborate on performance trade-offs, and develop physical design methodologies.

Design and verify FPGA hardware solutions for ultra-low latency applications, collaborating in a small team to develop innovative technologies.

The role involves design verification of IP/SoC with hands-on experience in verification methodologies, particularly UVM/OVM, and requires strong problem-solving skills in a fast-paced environment.

The Design Verification Engineer is responsible for constructing test benches, developing verification plans, debugging use-cases, and collaborating with design teams to ensure compliance with specifications.

Responsible for SI/PI design of 1.6T OSFP modules, conducting simulations and validations, defining design constraints, collaborating with teams, debugging, and contributing technical documentation.