Top Design Engineer Jobs in Bengaluru

Own end-to-end physical design and implementation flows from RTL to GDS for high-performance, low-power semiconductor and SoC designs. Responsibilities include synthesis, floorplanning, place and route, clock-tree synthesis, timing and power closure, EM/IR analysis, physical verification, DRC/LVS, methodology development, automation, and collaboration with microarchitecture teams to optimize power, performance, and area.

Design and optimize complex high-speed, multilayer PCBs from schematic through manufacturing files. Responsibilities include component placement, routing, signal and power integrity, noise mitigation, DFM/DFA, vendor collaboration, manufacturing support, project timeline management, and PCB testing and bring-up. The role also requires applying AI tools such as Claude and Gemini to improve engineering workflows. Experience with telecommunications, data storage, RF designs, and IPC certification is beneficial.

Designs and develops mechanical systems, enclosure structures, payload integration platforms, and mechanisms for aerospace or satellite applications. Performs FEA and structural simulations, creates CAD models and technical documentation, selects materials, oversees fabrication and assembly, coordinates environmental testing, and participates in design reviews to validate performance and compliance.

Lead RTL micro-architecture and implementation of ultra-low-power communication SoC blocks. Perform RTL linting, simulation, CDC/DRC checks, gate-level simulations, MBIST/DFT integration, ECOs, and power-aware verification using UPF and VCS-NLP. Collaborate with architects, analog teams, and handle timing closure and hardmacro integration.

Design and develop custom mechanical products, creating CAD models, drawings, bills of materials, tolerances, and engineering documentation. Support prototyping, testing, validation, and design-for-manufacturability efforts while collaborating with manufacturing and quality teams. Serve as a technical customer interface, translating requirements into engineering solutions, conducting technical reviews, and coordinating cross-functional customer programs.

Owns full-chip and block-level physical design from architecture through GDSII and production. Responsibilities include synthesis, place and route, clock tree synthesis, timing closure, formal equivalence verification, physical verification, DFT, ECO implementation, and collaboration with RTL and hard-macro IP vendors. The role supports complex SoC and silicon products for server, storage, and networking applications using advanced process technologies.

Design and develop electrolyzer systems, test stations, sheet metal components, mechanical assemblies, and associated hardware using SolidWorks. Prepare manufacturing drawings, BOMs, CAD documentation, and revisions for fabrication, machining, welding, laser cutting, and 3D printing. Collaborate with engineering teams and vendors to resolve design and manufacturing issues, incorporating feedback from assembly and testing.

Design, analyze, and tape-out low-power mixed-signal and RF circuits for wearable communication chips. Integrate analog IP into SoCs, verify and validate designs, collaborate with firmware/board/testing teams, and perform lab validation from schematic through layout and tape-out.

Design and develop mechanical components and enclosures using CAD. Create 3D models, assemblies, and manufacturing drawings. Support prototyping, vendor coordination, tolerance analysis, material selection, manufacturability, field testing, and documentation while collaborating with electronics and hardware teams.

Own physical implementation and sign-off of advanced semiconductor blocks from RTL through GDSII. Responsibilities include synthesis, floorplanning, placement, CTS, routing, timing closure, extraction, physical verification, EM/IR analysis, and PPA optimization. The role develops automation and methodology flows, resolves complex design-closure issues, collaborates across architecture and silicon teams, leads tapeout execution, and mentors engineers working on AI, CPU, GPU, memory, and other high-performance designs.

Develop and maintain mission design software for space situational awareness infrastructure. Responsibilities include orbital and mission simulations, computational optimization, sensitivity analysis, delta-V and link budgets, mission operations planning, sensor scheduling, software deployment, testing, technical reviews, and stakeholder presentations.

Lead design verification for 5G Open RAN SoC products, covering ARM Cortex subsystems, packet-processing blocks, and high-speed interfaces. Develop SystemVerilog/UVM testbenches, Python/C++ reference-model integrations, constrained-random tests, assertions, coverage, regressions, and hardware/software co-verification environments. Collaborate with architects, RTL, firmware, and systems teams while supporting emulation and FPGA prototyping. Drive verification planning, debugging, coverage closure, and transition of verification scenarios into firmware validation flows.

Senior design verification engineer responsible for verifying wireless DSP hardware blocks and 5G SoC designs. Develops UVM and SystemVerilog testbenches, integrates MATLAB and Python reference models, performs HW/SW co-verification, and executes directed and constrained-random testing. Responsibilities include coverage closure, assertions, regression analysis, debugging, verification planning, emulation, FPGA prototyping, and automated verification flows using scripting languages.

Perform RTL integration of IPs and subsystems into top-level SoCs, develop RTL wrappers, interconnect, clock/reset infrastructures; run lint/CDC/early synthesis checks; debug simulation and synthesis issues; automate and maintain integration flows with Python/Perl/Tcl; collaborate with design, verification, and physical design teams and contribute to design reviews and documentation.

Lead RF/analog/mixed-signal chip tapeouts from design through validation, integrate analog IPs into SoCs, prototype high-speed systems, mentor the team, validate silicon with test automation, and contribute to PCB design and firmware bring-up for wearable devices.

Lead microarchitecture and RTL development for complex connectivity IPs and subsystems. Translate system requirements into high-performance hardware designs, optimize latency, area, and power, and address flow control, buffering, arbitration, and error handling. Collaborate with verification, SoC integration, and physical design teams; support silicon bring-up and post-silicon debugging. Provide technical leadership through reviews, architecture ownership, and mentoring.

Design and verify Velaura’s Physical AI SoC from RTL blocks through complete hardware and software systems. Responsibilities include building SoC simulation environments, verifying boot, security, clock/reset, low-power, IO and memory subsystems, running CDC/RDC analysis, evaluating latency, bandwidth and QoS, and supporting coverage closure, sign-off and tape-out. The role requires extensive SoC verification experience with SystemVerilog, UVM, C/C++, CPU-based platforms, PCIe, LPDDR, UPF and low-power verification flows.

Own functional verification of custom CPU units from test planning through coverage closure. Build SystemVerilog and UVM environments with C/C++, stimulus, checkers, assertions, trackers, and coverage. Verify instruction execution, caches, memory ordering, coherence, exceptions, privilege behavior, and performance. Execute regressions, support emulation and FPGA prototyping, enable pre-silicon software bring-up, and debug hardware-software issues across multidisciplinary teams.

Develop and execute verification strategies for complex SoC hardware, including compute engines, memory systems, interconnects, processors, DMA, and system software interactions. Build SystemVerilog and UVM environments, assertions, checkers, scoreboards, and formal verification workflows. Analyze performance, latency, bandwidth, QoS, and real-time behavior; support emulation, FPGA prototyping, pre-silicon bring-up, post-silicon debugging, and hardware-software root-cause analysis.

Develop and execute verification strategies for complex Physical AI SoC components and full HW/SW systems. Build SystemVerilog and UVM environments, assertions, checkers, scoreboards, and formal verification flows. Verify processors, memory, interconnects, DMA engines, and accelerators for correctness, performance, safety, and reliability. Lead emulation, FPGA prototyping, pre-silicon validation, post-silicon debugging, root-cause analysis, and system-level workload testing while collaborating across architecture, RTL, software, and systems teams.

Own verification of custom AI accelerator hardware, including matrix and vector compute engines. Develop SystemVerilog and UVM environments, reference models, assertions, checkers, coverage, and regression infrastructure. Verify numerical precision, quantization, data flow, performance, and reliability across RTL blocks and subsystems. Collaborate with architecture, RTL, software, compiler, and runtime teams through emulation and silicon bring-up.

Creates detailed 2D drawings and 3D CAD models, collaborates with engineers and architects, manages technical documentation and drawing databases, supports design reviews, and identifies innovative solutions. The role requires adaptability, assertive communication, attention to detail, teamwork, and willingness to handle varied responsibilities in a fast-paced startup environment.

Design and develop Class I and II medical devices from concept through commercialization. Responsibilities include CAD modeling, manufacturing drawings, DFMEA, risk assessment, DFM/DFA, prototyping, verification and validation testing, BOMs, engineering documentation, ECN/ECR management, quality issue resolution, and manufacturing support. The role collaborates with industrial design, electronics, manufacturing, quality, and regulatory teams while ensuring compliance with medical device standards.

Develop and maintain production-ready electrical schematics, PCB layouts, drawing templates, component libraries, BOMs, and approved alternate parts lists. Review designs for integrity, manufacturability, testability, and documentation completeness. Coordinate with procurement, manufacturing, quality, and engineering teams to resolve component and production issues while maintaining engineering changes, revisions, and accurate product records.

Lead architecture and RTL development for UALink IP and subsystems. Translate protocol requirements into scalable hardware architectures, design high-bandwidth low-latency datapaths and control logic, and optimize performance, power, area, and latency. Develop and review SystemVerilog RTL, collaborate with verification, physical design, integration, and firmware teams, debug complex issues, contribute to architecture decisions, and mentor engineers.