Top Design Engineer Jobs in Bengaluru, KA

Join Marvell as a Principal Physical Design Engineer in Hyderabad, India. Work on physical design and methodology for next-generation high-performance processor chips. Collaborate with global teams, maintain and enhance Place and Route Flow, and drive successful tape-outs. Must have a Bachelor's or Master's degree in relevant fields and 12+ years of experience in physical design.

Seeking a Sr Staff Mask Design Engineer with 15 years of experience in Analog layout design and associated flows for DRC, LVS, and packaging. Responsible for driving design innovation, floor planning, and layout for analog circuits in the automotive power sector. Must have mentoring experience and expertise in IC processing and CAD tools.

Infinera is seeking an experienced Optical Engineer to join their Hardware design group in Bengaluru, India. This role involves hands-on work with system-level optical communication hardware and components. The Optical Engineer will play a key role in designing and characterizing high-complexity DWDM equipment for Metro, Long-Haul, Ultra-Long-Haul applications, and Coherent Transceivers.

As a Senior Digital Design Engineer, you will design ARM processor subsystems, smaller IP blocks for SoCs, and integrate components like NOCs, DMA, PCI, and Ethernet, while coordinating with stakeholders on automotive applications.

Join the Power Design Team at Renesas Electronics America working on next-generation IC products for consumer, industrial, and automotive power products. Responsibilities include analog and power design, block-level design, interface with various teams, simulation, and test support. Requires BSEE (MSEE pref.) with 20+ years experience in Analog design engineering role.

The Digital Design Engineer will be responsible for designing optimized digital blocks, developing TCL scripts, supporting DFT strategy, planning verification, interfacing with P&R for design hand-offs, and producing documentation. The role requires ownership of deliverables and continuous improvement in work practices.

Join Marvell as a Senior Staff RTL Design Engineer working on ultra-dense and performance Static Random Access Memory (SRAM) memory compilers.

Design world-class hardware, integrate with software and mechanical housings, have cross-functional engineering influence, take technical ownership for hardware development, support technology readiness, build methodology and processes, and support proposals.

As a Senior Manager ASIC Design Engineer at Infinera, you will be responsible for managing the design execution of ASIC and FPGA projects. You will work closely with various teams to estimate scope of work, monitor project execution, and provide leadership to a team of Engineers.

Work with the Cadence global IC design team to develop semiconductor IP for top electronic product companies, ensuring continuous quality improvement and adherence to quality procedures.

Lead Design Engineer responsible for creating and maintaining functional verification environments, defining verification strategies, and collaborating with cross-functional teams. Requires expertise in Verilog, SystemVerilog, UVM methodology, RTL, and various verification domain skills. Desirable skills include power-aware RTL, formal verification, gate-level simulations, and exposure to automotive IP verification.

Looking for a Senior Principal RTL Design Engineer with 12+ years of ASIC design experience. Proficiency in Verilog coding, RTL design, and various interface protocols. Must have knowledge of RTL checks and synthesis flow.

Join a growing team at Cadence as a Sr Principal Design Engineer, responsible for leading the Design for Test activities for next-gen SoCs. Define DFT architecture, implement verification logic, collaborate with teams, and work on silicon bring up. Ideal candidate has 8-15+ years of experience with key DFT concepts and working knowledge of Verilog coding

Cadence is looking for a passionate Layout Design professional with 2-14 years of experience in Analog Layout and SerDes IP. The role involves working on cutting edge FinFET technologies and collaborating with Tier-1 customers. Responsibilities include hands-on layout experience in various analog IPs, knowledge of layout effects on circuits, understanding of DSM technology, and communication skills. Scripting and automation experience is a plus.

Principal DFT Design Engineer responsible for mentoring junior engineers, driving innovation/automation, working with cross-functional teams, and leading DFT methodology advancements to improve quality and reliability.

Design Engineer II at Cadence with 2-4 years (with Btech) or 1-2 years (with Mtech) of experience in Post-Silicon Physical Layer Electrical Validation. Responsibilities include deep physical layer electrical validation on high-speed SERDES protocols, using lab equipment, managing small teams, leading post-silicon validation efforts, FPGA design, PCB schematic and layout design, and more.

Senior Digital Design Engineer focusing on high-performance analog-to-digital and digital-to-analog converters. Responsibilities include RTL design, verification, synthesis, timing closure, and P&R flow for digital controllers in cutting-edge technologies.