Top Design Engineer Jobs in Bengaluru

Perform full-chip functional verification including RTL-to-RTL and RTL-to-netlist FV, execute Conformal ECO flows, and debug non-equivalence issues for Qualcomm chip designs. Collaborate on verification tasks onsite in Bangalore.

Perform IC physical design from netlist to GDS: floorplan, implementation, timing closure, STA, ECOs, verification (FV/CLP/PV). Handle medium/complex blocks (~400K–800K instances), debug congestion, high-utilization and multi-voltage designs. Use EDA tools (ICC/ICC2, Synopsys STARXT/PTSI, Olympus/Calibre, Rehawk). Perl/Tcl scripting, IR-drop analysis and low-power design are desirable.

The Mechanical Drafting Engineer will prepare detailed 2D drawings, 3D models, and manufacturing documentation, coordinate with teams, and ensure accurate engineering design.

Design and develop mechanical systems for aerospace applications, focusing on ruggedness and lightweight mechanisms, while collaborating with diverse teams.

The Lead RF Hardware Design Engineer will lead the design and development of RF hardware for satellite communication systems, guiding a team through complex design challenges.

Design and develop mechanical components and assemblies from requirements using CAD (Onshape, SolidWorks/Fusion 360). Create 3D models, manufacturing drawings, and prototypes; perform tolerance analysis, material selection, manufacturability reviews, vendor coordination, and field validation while integrating with electronics and hardware teams.

The Junior Mechanical Design Engineer will support the design and development of mechanical subsystems, create 3D CAD models, contribute to structural analysis, and assist in prototyping and testing.

Design and optimize custom digital logic for UAVs focusing on motion control, neural network acceleration, and real-time computation. Responsibilities include RTL architecture design, collaboration with engineers, integration of custom RTL blocks, and optimization for performance and reliability.

Design, analyze, and tape-out low-power mixed-signal and RF circuits for wearable communication chips. Integrate analog IP into SoCs, verify and validate designs, collaborate with firmware/board/testing teams, and perform lab validation from schematic through layout and tape-out.

Design and lead development of miniaturized PCBs for wearable devices using custom Wi-R ICs and COTS components. Create schematics and layouts, perform board-level testing and debugging, collaborate on packaging, and support prototype validation and test automation.

Lead RTL micro-architecture and implementation of ultra-low-power communication SoC blocks. Perform RTL linting, simulation, CDC/DRC checks, gate-level simulations, MBIST/DFT integration, ECOs, and power-aware verification using UPF and VCS-NLP. Collaborate with architects, analog teams, and handle timing closure and hardmacro integration.

The Microarchitect and RTL Design Engineer will design microarchitectures, ensure optimal performance in RTL coding, and collaborate with software and verification teams to meet project requirements.

Seeking a Physical Design Engineer to manage RTL to GDS flows, collaborate on performance trade-offs, and develop physical design methodologies.

The ASIC Design Engineer will develop SoCs, micro-architecture design, RTL coding, optimization, and collaborate with multiple teams for ASIC development.

Senior Mechanical Design Engineer responsible for HVAC system design, 2D/3D modeling, detailing, BIM construction documentation, Trane Trace calculations, QA/QC, and client coordination to deliver CAD/BIM projects for commercial, residential, sports, office, hospital and mixed-use buildings.

Lead mechanical design of electro-mechanical and automotive mechanisms from concept through production. Create CAD models, run FEA and tolerance analyses, prototype and validate designs, collaborate with electronics and manufacturing, manage supplier handoffs, perform root-cause analysis, and ensure manufacturability, reliability, and safety.

Design high-performance analog-to-digital and digital-to-analog converters, evaluate silicon, and oversee layout in advanced CMOS processes.

Design and verify digital datapaths for high-performance ADCs and DACs using RTL, assist with synthesis and timing closure, and automation through scripting.

The Senior Analog IC Design Engineer will work on high-speed analog designs, collaborate with teams for implementation, and analyze performance tradeoffs.

Design and verify high-performance digital and mixed-signal ICs, focusing on RTL design, behavioral modeling, and digital control circuits.

The Senior Digital Design Engineer will design, verify, and validate digital architecture for automotive and space applications, focusing on RTL and FPGA.

Lead block-level physical implementation from synthesis and floorplan through CTS, routing, and sign-off. Optimize PPA via deep timing, power, and congestion analysis, automate flows with Tcl/Python, resolve DRC/LVS/IR/timing issues, and collaborate with RTL/DFT teams to left-shift constraints and ensure clean GDSII tape-outs.

Lead full RTL-to-GDSII physical design for sub-5nm SoCs: own full flow, optimize PPA, build scalable push-button methodology, remove execution bottlenecks, and collaborate with RTL/Architecture/DFT/foundry/EDA teams.

Join SPAN as a Hardware Design Engineer to design and test electrical components, focusing on PCBAs and renewable energy applications, collaborating with cross-functional teams.

The role involves digital RTL design of SoCs, contributing to architecture and driving methodologies for successful chip designs, while collaborating with various teams.