The CPU Core Feature Verification and Debug Engineer at Tenstorrent is responsible for ISA and micro-architectural verification. The role involves functional verification, testplan development, stimulus creation, regression debugging, and ensuring high-quality delivery of CPU core/cluster.

Define verification plans, develop DV environments in System Verilog, create and execute test plans, demonstrate expertise in UVM methodologies, perform functional verification at the RTL level, develop UVCs from scratch, experience with Cache and NOC Interconnect verification, knowledge of bus protocols like AXI and CHI.