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The Principal Engineer will define micro-architectures, implement RTL coding, collaborate with various teams, and mentor junior engineers in semiconductor solutions.

The Senior Staff Power Design Engineer will work on low power design and physical implementation for ASICs, collaborating across teams to optimize power and perform physical verification.

Responsible for implementing and validating DFT/Test on complex ASIC/SoC designs while mentoring a team and enhancing DFT methodologies.