Top Tech Jobs & Startup Jobs in Bengaluru, KA

Seeking a Senior Manager for the Static Timing Analysis (STA) function to lead a team of engineers responsible for timing performance and integrity of semiconductor designs. Requires deep STA expertise, leadership skills, and vision for process improvement. Responsibilities include team management, developing advanced STA methodologies, collaborating with cross-functional teams, automation of timing analysis processes, and project management. Qualifications include a Bachelor's or Master's degree in relevant field and 15 years of STA experience, with at least 3 years in a leadership role.

Expertise in ASIC verification, System Verilog, UVM, and Verilog. Leading a team of engineers, defining verification plans, creating testbenches, and conducting gate level simulations. Knowledge of serial and memory protocols, scripting languages, and continuous process improvement.

Seeking a Physical Design Implementation Lead with expertise in Static Timing Analysis to lead advanced semiconductor design projects and drive successful implementation of integrated circuits. Responsibilities include leading physical design efforts, performing static timing analysis, collaborating with cross-functional teams, and optimizing power, performance, and area.

Seeking a Principal Engineer with strong expertise in ASIC development and DFT to join a dynamic team working on next-generation Flash Controllers. Responsibilities include defining and implementing industry-leading DFT solutions, collaborating with cross-functional teams, and ensuring quality and timelines are met.

Principal Engineer responsible for developing C++/SystemC models for complex ASIC IPs, SOCs, and Flash Memories. Create system level tests, verify models, and provide timely support for software bring-up. Requires 8-12 years of experience and proficiency in SystemC, TLM, C++, and embedded system test development.

Seeking a Senior Technologist for ASIC Development Engineering with 10-20 years of experience in SOC design and implementation flow. Responsibilities include defining requirements, reviewing product and FW requirements, evaluating implementation solutions, supporting ASIC organization teams, and finding opportunities for design improvement. Qualifications include a Bachelor/Master degree in Electronics/VLSI/Micro-Electronics Engineering, 10+ years of ASIC Design/Architecture experience, RTL design experience, and knowledge in various aspects of SOC design and verification.

Seeking a highly skilled Analog/IO Layout Engineer with 5-10 years of experience to design and implement complex analog and mixed-signal IC layouts. Strong background in analog/IO design principles, hands-on experience with layout tools, and a passion for solving challenging technical problems.