Top Python Jobs in Bengaluru

Lead verification strategy and execution for complex connectivity IPs and SoCs (CXL/PCIe/Ethernet). Architect and develop UVM/SystemVerilog environments, drive coverage-driven constrained-random verification, debug RTL/protocol/timing issues, build reusable VIP, and mentor teams to achieve first-pass silicon success.

Lead RTL design and implementation of complex digital IPs and SoC subsystems for high-performance connectivity products. Own specification-to-silicon flow, design synthesizable Verilog/SystemVerilog, develop datapaths, control logic and protocol engines (CXL, PCIe, Ethernet, AXI). Collaborate with verification, physical design, firmware, and system teams; support synthesis/lint/STA/DFT, debug silicon issues, and mentor engineers.

Lead verification of complex IPs and SoC subsystems from spec through tape-out. Own verification planning, UVM/SystemVerilog environment development, test execution, coverage closure, debugging, root-cause analysis, and sign-off. Collaborate with architecture, design, firmware, emulation, and validation teams and mentor engineers to ensure high-quality, first-pass silicon.

Design, integrate, validate, and optimize hardware platforms for AI training and inference. Benchmark and troubleshoot server, GPU, networking, and storage performance. Build reliable rack-scale infrastructure, develop validation and diagnostics, support deployments, automate provisioning and monitoring, and collaborate with software, platform, and customer teams to deliver production-ready AI infrastructure.

Design, build, and operate scalable, secure network infrastructure across cloud and on-premises environments to support AI workloads. Architect hybrid/multi-cloud networking, ensure high availability and security, troubleshoot performance issues, automate provisioning with IaC, and improve observability and disaster recovery. Support customer deployments and incident response.

Design, build, and operate Aion's virtualization platform for AI workloads across cloud, hybrid, and on-prem environments. Architect secure, high-performance virtualization infrastructure, implement compute/resource scheduling (CPU, memory, storage, GPU), optimize performance and scaling, automate provisioning and lifecycle management, ensure multi-tenant security and enterprise compliance, and build observability for infrastructure reliability while collaborating with platform and customer teams.

Design, implement, and support enterprise Esri-based geospatial systems. Manage ArcGIS platforms and geodatabases, automate workflows with Python, build web mapping tools, process drone/backpack Lidar, troubleshoot systems, collaborate with global teams, and produce technical documentation to support disaster response and environmental operations.

Work on production backend APIs and services for an AI platform used by semiconductor manufacturers. Build scalable, low-latency systems, ensure multi-tenant isolation, write well-tested code, and collaborate with senior engineers while using AI coding tools and deployment pipelines. High-ownership internship with potential PPO for top performers.

Lead DevOps/SRE responsible for designing and operating GCP infrastructure, IaC (Terraform), Kubernetes/GKE management, CI/CD and GitOps pipelines, observability, SLO/SRE practices, incident response, cost optimization, security best practices, and mentoring other DevOps engineers.

Design, implement, maintain, and troubleshoot enterprise LAN/WAN/WLAN/cloud data center networks. Manage Layer 2/3 routing and switching, routing protocols (BGP/OSPF/EIGRP), firewalls and network security, monitoring, capacity planning, HA and DR, cloud connectivity, documentation, and on-call incident response. Collaborate with infrastructure, security, and application teams for deployments and upgrades.

Lead QA strategy and hands-on test automation for an AI-first SaaS product. Design and maintain Playwright-based end-to-end frameworks, API tests, CI/CD integration, test data/environment strategies, quality metrics, and mentor QA engineers while promoting shift-left practices.

The Design Verification Engineer ensures functional correctness of IPs and SoCs by developing verification environments, driving coverage closure, and automating tasks to enhance productivity.

The CAD/Flow Methodology Development leader will define and scale EDA infrastructure, automate design flows, debug issues, and establish metrics for silicon delivery efficiency in cross-functional environments.

As a Design Team Member, you will implement digital blocks to full-chip designs, focusing on physical design constraints and ensuring manufacturability by coordinating with various engineering teams.

Design and implement backend microservices on AWS using Python or other backend frameworks. Build RESTful APIs, manage containerized deployments with Docker, work with SQL/PostgreSQL, and participate in agile development to deliver scalable backend systems.

Design and implement robotics software using ROS1/ROS2 for path/motion planning, SLAM, simulation (Gazebo), and hardware interfacing. Develop drivers, algorithms in C++/Python, own features end-to-end, ensure quality through testing, and lead complex feature deliveries.

Full‑stack engineer to own features end‑to‑end: build scalable backends (Go, Python, Node.js), responsive Flutter and React.js frontends, CI/CD pipelines, app store deployments, and real‑time database/data‑flow for sensor/connected‑device products.

Design and implement DFT solutions (scan, ATPG, MBIST), use industry DFT tools, develop simulation and integration specs, script automation, and debug simulations and JTAG.

The role involves digital RTL design of SoCs, contributing to architecture and driving methodologies for successful chip designs, while collaborating with various teams.

As a Senior Digital Verification Engineer, you will undertake system and block-level verification, develop test plans, create testbenches and verification infrastructure, and collaborate closely with design teams to ensure the functionality of AI hardware components.

The role involves implementing DFT features on Mythic's SoCs, contributing to methodology development, and collaborating with design teams throughout the design cycle.

The role involves ownership of physical design processes, collaboration in various design areas, mentoring, and optimizing performance, power, and area in advanced nodes.

Lead DFT implementation and verification for ASIC/SoC designs, focusing on methodologies like MBIST, IJTAG, Scan, and ATPG while collaborating with cross-functional teams.

As a Senior Backend Engineer, you will design and maintain scalable software solutions, embrace innovation with AI tools, and ensure high-quality engineering practices.

Design, build, and maintain backend APIs and services for a real-time supply chain visibility platform. Own system architecture, real-time event ingestion, data normalization, ML integration, monitoring, and production debugging while collaborating with Product and Data Science to deliver scalable, high-availability features.