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The role involves leading the RTL design and verification team for high-performance CPU microarchitectures, focusing on AI/ML applications, while ensuring quality and alignment with organizational goals.

Design for Test Engineer responsible for implementing DFT features in RTL, conducting test coverage analysis, and supporting silicon bring-up. Collaborates with engineers on advanced DFx techniques for high-performance AI/ML designs.

The Senior Physical Design Engineer will lead physical design tasks, including synthesis, timing closure, and power optimization for high-performance chip designs.