Top Tech Jobs & Startup Jobs in Bengaluru, KA

Write, edit, and prepare product documentation for semiconductor IPs and SoC designs. Collaborate with engineering and product teams to ensure accuracy and completeness of documentation. Convert content to DITA XML format. Requires 5-10 years of technical writing experience and a BA or BS degree in a relevant technical field or English/Technical Communications.

Seeking a Senior DFT Engineer with 5-15 years of experience in SoC/ASIC Digital Design and expertise in Design for Test (DFT). Responsibilities include scan chain insertion, compression scan technologies, MBIST, ATPG, and verification of testbenches.

Ensure availability, reliability, scalability, and manageability of data storage environment. Collaborate with stakeholders to meet data and storage requirements. Monitor and analyze system performance to optimize Storage environments. Provide technical expertise, support, and recommendations for storage infrastructure improvement. Manage capacity and performance of storage infrastructure. Assist with backup and recovery procedures. Participate in change control activities.

Seeking a Principal Design Verification Engineer with 8+ years of experience in Design Verification using SystemVerilog and UVM. Must have a strong background in functional verification fundamentals and experience verifying complex designs.

Lead Physical Design Design Engineer responsible for DDR PHY IP & Testchip Physical Design in sub 7nm tech nodes. Key responsibilities include owning physical design blocks, optimizing power/performance, and contributing to design methodology. Required skills in Netlist-GDS physical design, scripting, and experience in Cadence tools.

Design Engineer II at Cadence with 2-4 years (with Btech) or 1-2 years (with Mtech) of experience in Post-Silicon Physical Layer Electrical Validation. Responsibilities include deep physical layer electrical validation on high-speed SERDES protocols, using lab equipment, managing small teams, leading post-silicon validation efforts, FPGA design, PCB schematic and layout design, and more.

Immediate opening for a Design Engineering Manager at Cadence Design Systems in Bangalore. Responsibilities include leading pre and post silicon Physical Layer Electrical Validation efforts. Looking for candidates with 6-10 years of experience in the field and expertise in High Speed SERDES protocols like PCIe, USB, DP, ethernet, and more.