Top Engineering Jobs in Bengaluru, KA

Seeking a skilled ASIC Power Architect to define Multi Power Domain architectures in SoC with a focus on Low-Power states. Responsibilities include power analysis, optimization, defining methodologies, guiding implementation, and collaborating with cross-functional teams to refine Power Architecture.

Lead the architecture and design of NAND development, provide technical leadership, mentorship, and innovation, collaborate with cross-functional teams to develop cutting-edge storage solutions, and drive system level architecture decisions.

Seeking a Principal Engineer with strong expertise in ASIC development and DFT to join a dynamic team working on next-generation Flash Controllers. Responsibilities include defining and implementing industry-leading DFT solutions, collaborating with cross-functional teams, and ensuring quality and timelines are met.

Seeking a Physical Design Lead with expertise in full-chip RDL and bump layouts for semiconductor products. Responsibilities include design optimization, team management, collaboration with packaging and manufacturing engineers, and integration with chip package. Ensure robust design solutions and compliance with project specifications.

Seeking a Senior Manager for the Static Timing Analysis (STA) function to lead a team of engineers responsible for timing performance and integrity of semiconductor designs. Requires deep STA expertise, leadership skills, and vision for process improvement. Responsibilities include team management, developing advanced STA methodologies, collaborating with cross-functional teams, automation of timing analysis processes, and project management. Qualifications include a Bachelor's or Master's degree in relevant field and 15 years of STA experience, with at least 3 years in a leadership role.

Principal Engineer responsible for developing C++/SystemC models for complex ASIC IPs, SOCs, and Flash Memories. Create system level tests, verify models, and provide timely support for software bring-up. Requires 8-12 years of experience and proficiency in SystemC, TLM, C++, and embedded system test development.

Expertise in ASIC verification, System Verilog, UVM, and Verilog. Leading a team of engineers, defining verification plans, creating testbenches, and conducting gate level simulations. Knowledge of serial and memory protocols, scripting languages, and continuous process improvement.

Seeking a Physical Design Implementation Lead with expertise in Static Timing Analysis to lead advanced semiconductor design projects and drive successful implementation of integrated circuits. Responsibilities include leading physical design efforts, performing static timing analysis, collaborating with cross-functional teams, and optimizing power, performance, and area.