Top Python Jobs in Bengaluru

The Application Solution Architect will design scalable data architectures and lead a team of data engineers. This role involves managing data engineering projects through collaboration with various stakeholders, ensuring data quality and security, and integrating new technologies to enhance data practices.

The Product Engineer II will develop Conformal expertise within regional teams, lead deployment of Conformal products, conduct training and seminars, capture customer feedback for tool enhancements, and collaborate with R&D to address customer issues. A strong background in ASIC implementation and programming skills in Tcl and Python is required.

The Sr Solutions Engineer will develop Pegasus DRC/LVS runsets, automate regression tests, detect issues, and generate validation reports. They will also support customer tool bugs and enhancements, and collaborate with the R&D team.

The Lead Solutions Engineer will review design specifications, develop verification strategies and test plans, and create constrained random verification environments. Responsibilities include writing functional tests and assertions to meet verification goals, with a focus on SOC verification using C-based test cases and various protocols.

The Lead Design Engineer at Cadence will develop firmware for various memory interfaces, collaborate with hardware designers and architects, deduce co-verification plans with the verification team, and support debugging efforts on simulations and silicon boards.

The Lead Design Engineer will perform pre and post silicon Physical Layer Electrical Validation on High Speed SERDES IP. Responsibilities include designing hardware/software infrastructure, implementing rigorous test suites, debugging silicon issues, and generating test reports.

As a Lead Support Application Engineer at Cadence in Bangalore/Noida, you will provide technical support for IC level Power System analysis products, work closely with customers to debug complex issues, and guide them with implementing software in their design methodologies. You will have opportunities for technical knowledge acquisition, exposure to industry design practices, and contribute to key technology solutions. Join a diverse team passionate about innovation and technology.

Join a growing team at Cadence as a Sr Principal Design Engineer, responsible for leading the Design for Test activities for next-gen SoCs. Define DFT architecture, implement verification logic, collaborate with teams, and work on silicon bring up. Ideal candidate has 8-15+ years of experience with key DFT concepts and working knowledge of Verilog coding