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The Principal Engineer will oversee chiplet architecture and design, focusing on RTL design, microarchitecture documentation, and hardware quality checks throughout the ASIC development cycle.

The role involves microarchitecting, RTL design of SoC subsystems/IP blocks, collaborating with various teams for successful ASIC development and tapeout.

Manage the design team for SoC development, providing technical support and ensuring project goals are met through collaboration with cross-functional teams.

As an RTL Design Engineer at Alphawave Semi, you'll engage in the complete ASIC development cycle, responsible for microarchitecture coding, documentation, and collaborating with verification and physical design teams to ensure quality SoC designs.

The Staff Engineer will lead SOC EMIR analysis, collaborate with teams for design changes, mentor juniors, and influence analysis workflows.

The role involves hands-on ASIC physical design and verification, managing development flows, mentoring, and ensuring integration of designs.

The Senior Engineer I - DFT will lead DFT strategy, develop verification methodologies, automate test bench creation, and ensure timing checks for SoCs.