Top Design Engineer Jobs in Bengaluru

Perform IC physical design from netlist to GDS: floorplan, implementation, timing closure, STA, ECOs, verification (FV/CLP/PV). Handle medium/complex blocks (~400K–800K instances), debug congestion, high-utilization and multi-voltage designs. Use EDA tools (ICC/ICC2, Synopsys STARXT/PTSI, Olympus/Calibre, Rehawk). Perl/Tcl scripting, IR-drop analysis and low-power design are desirable.

Perform full-chip functional verification including RTL-to-RTL and RTL-to-netlist FV, execute Conformal ECO flows, and debug non-equivalence issues for Qualcomm chip designs. Collaborate on verification tasks onsite in Bangalore.

Design and develop mechanical systems for aerospace applications, focusing on ruggedness and lightweight mechanisms, while collaborating with diverse teams.

The Lead RF Hardware Design Engineer will lead the design and development of RF hardware for satellite communication systems, guiding a team through complex design challenges.

Develop and execute block- and system-level verification plans for complex SoC and silicon designs using PCIe and CXL protocols. Create UVM test sequences, assertions, cover properties, randomized constraints, and VIP abstraction layers. Analyze coverage and system-level performance, debug failures with RTL designers, and verify Physical, Link, and Transaction Layers across PCIe/CXL endpoint and root-complex implementations.

The Microarchitect and RTL Design Engineer will design microarchitectures, ensure optimal performance in RTL coding, and collaborate with software and verification teams to meet project requirements.

Designs and reviews electrical systems including switchgear, transformers, MCCs, cables, lighting, grounding, and lightning protection. Prepares load, cable, interconnection, and motor-starting schedules, along with electrical layouts and single-line diagrams. Supports electrical installation, testing, commissioning, site execution, safety, quality, and schedule compliance. Coordinates contractors, subcontractors, clients, site teams, and other departments, and travels to client offices or construction sites to resolve technical queries.

Designs electrical and instrumentation systems for process industries, including SLDs, cable trays, transformer and cable sizing, PCC/MCC schemes, lighting, and lightning protection. Selects PLC/DCS automation systems and electrical equipment, prepares GA and layout drawings in AutoCAD, reviews vendor drawings and documents, conducts vendor inspections, and visits customer sites for meetings and troubleshooting.

Lead full-chip or large-block physical implementation from netlist to GDSII. Drive floorplanning, placement, CTS, routing, STA timing closure, DRC/LVS/EM/IR signoff, ECOs, hard-macro integration, PPA optimization, and automation scripting while collaborating with RTL, architecture, verification, and foundry teams.

The role involves ownership of physical design processes, collaboration in various design areas, mentoring, and optimizing performance, power, and area in advanced nodes.

Own end-to-end UI/UX and frontend implementation: design user flows, craft high-fidelity prototypes, build responsive React+TypeScript interfaces, implement scalable component architecture, integrate with REST/GraphQL APIs, optimize performance, and collaborate with backend and product teams in a regulated life-sciences context.

The Design Verification Engineer is responsible for constructing test benches, developing verification plans, debugging use-cases, and collaborating with design teams to ensure compliance with specifications.

Design and verify FPGA hardware solutions for ultra-low latency applications, collaborating in a small team to develop innovative technologies.

Responsible for SI/PI design of 1.6T OSFP modules, conducting simulations and validations, defining design constraints, collaborating with teams, debugging, and contributing technical documentation.

Lead development, optimization, and verification of digital silicon IP from model to bring-up. Create and maintain specs, block diagrams, and documentation. Characterize IP performance using industry-standard tools and flows, including FPGA simulation and emulation. Collaborate with architecture, physical design, and software teams and lead verification engineers.

Design and implement RTL and microarchitectural components for SoC/IP using SystemVerilog/Verilog. Optimize PPA, collaborate with verification and physical design teams, support integration, timing closure, simulation, GLS, and silicon bring-up, and contribute to design documentation and reviews.

As a Demo Engineer, you support pre-sales by designing AI-driven demos and proof of concepts, collaborating closely with teams to showcase Cresta's capabilities.