Top Design Engineer Jobs in Bengaluru

The Hardware Design Engineer will design, develop, and test electronics circuits and systems, collaborating with teams for enhanced product performance.

Lead RTL Design Engineer for wireless baseband architecture, overseeing design teams, implementing RTL designs, and ensuring adherence to methodologies.

Design and implement RTL blocks for wireless systems, perform synthesis on FPGAs, and collaborate with software and hardware teams.

Join a startup as a Physical Design Engineer, focusing on RTL-to-GDSII implementation, performance optimization, and AI-driven automation.

Design and develop mechanical components and enclosures using CAD. Create 3D models, assemblies, and manufacturing drawings. Support prototyping, vendor coordination, tolerance analysis, material selection, manufacturability, field testing, and documentation while collaborating with electronics and hardware teams.

Design and optimize custom digital logic for UAVs focusing on motion control, neural network acceleration, and real-time computation. Responsibilities include RTL architecture design, collaboration with engineers, integration of custom RTL blocks, and optimization for performance and reliability.

The ASIC Design Engineer will develop SoCs, micro-architecture design, RTL coding, optimization, and collaborate with multiple teams for ASIC development.

The role involves leading a team of Physical Design engineers in delivering high-performance silicon products while ensuring adherence to timing, power, and area requirements. Responsibilities include technical leadership, hands-on ownership of critical blocks, automation development, and stakeholder management to meet project milestones.

Perform full-chip functional verification including RTL-to-RTL and RTL-to-netlist FV, execute Conformal ECO flows, and debug non-equivalence issues for Qualcomm chip designs. Collaborate on verification tasks onsite in Bangalore.

Perform IC physical design from netlist to GDS: floorplan, implementation, timing closure, STA, ECOs, verification (FV/CLP/PV). Handle medium/complex blocks (~400K–800K instances), debug congestion, high-utilization and multi-voltage designs. Use EDA tools (ICC/ICC2, Synopsys STARXT/PTSI, Olympus/Calibre, Rehawk). Perl/Tcl scripting, IR-drop analysis and low-power design are desirable.

Design and develop mechanical systems for aerospace applications, focusing on ruggedness and lightweight mechanisms, while collaborating with diverse teams.

The Lead RF Hardware Design Engineer will lead the design and development of RF hardware for satellite communication systems, guiding a team through complex design challenges.

Perform RTL integration of IPs and subsystems into top-level SoCs, develop RTL wrappers, interconnect, clock/reset infrastructures; run lint/CDC/early synthesis checks; debug simulation and synthesis issues; automate and maintain integration flows with Python/Perl/Tcl; collaborate with design, verification, and physical design teams and contribute to design reviews and documentation.

Lead RF/analog/mixed-signal chip tapeouts from design through validation, integrate analog IPs into SoCs, prototype high-speed systems, mentor the team, validate silicon with test automation, and contribute to PCB design and firmware bring-up for wearable devices.

Responsible for SI/PI design of 1.6T OSFP modules, conducting simulations and validations, defining design constraints, collaborating with teams, debugging, and contributing technical documentation.

The role involves leading SoC verification projects, utilizing methodologies like UVM/OVM, and fostering a collaborative team culture focused on AI innovations.

Lead full-chip or large-block physical implementation from netlist to GDSII. Drive floorplanning, placement, CTS, routing, STA timing closure, DRC/LVS/EM/IR signoff, ECOs, hard-macro integration, PPA optimization, and automation scripting while collaborating with RTL, architecture, verification, and foundry teams.

Design and integrate RF systems for ground and space applications: define system requirements and architecture, select components, perform RF simulations, carry out component characterization, integrate and validate hardware using RF test equipment, and collaborate with cross-functional teams to meet system specifications.

As a Demo Engineer, you support pre-sales by designing AI-driven demos and proof of concepts, collaborating closely with teams to showcase Cresta's capabilities.

The role involves ownership of physical design processes, collaboration in various design areas, mentoring, and optimizing performance, power, and area in advanced nodes.

The Design Verification Engineer is responsible for constructing test benches, developing verification plans, debugging use-cases, and collaborating with design teams to ensure compliance with specifications.

The role involves design verification of IP/SoC with hands-on experience in verification methodologies, particularly UVM/OVM, and requires strong problem-solving skills in a fast-paced environment.

Design and verify FPGA hardware solutions for ultra-low latency applications, collaborating in a small team to develop innovative technologies.

Design and implement RTL and microarchitectural components for SoC/IP using SystemVerilog/Verilog. Optimize PPA, collaborate with verification and physical design teams, support integration, timing closure, simulation, GLS, and silicon bring-up, and contribute to design documentation and reviews.

Lead development, optimization, and verification of digital silicon IP from model to bring-up. Create and maintain specs, block diagrams, and documentation. Characterize IP performance using industry-standard tools and flows, including FPGA simulation and emulation. Collaborate with architecture, physical design, and software teams and lead verification engineers.