Top Design Engineer Jobs in Bengaluru

The role involves digital RTL design of SoCs, contributing to architecture and driving methodologies for successful chip designs, while collaborating with various teams.

The Hardware Design Engineer will design, develop, and test electronics circuits and systems, collaborating with teams for enhanced product performance.

Lead RTL-to-GDSII implementation on advanced-node digital designs, driving PPA and quality-of-results. Own flows, debug complex issues, collaborate with CAD/design/program teams, mentor juniors, adopt new tools and ML techniques, and engage EDA vendors to resolve root causes.

Design and own end-to-end RF systems for radar/defence: architecture, waveform and receive-chain design, RF front-ends, antennas and arrays, calibration, lab/field validation, and production hardening. Use EM and circuit simulation tools, RF lab instruments, and scripting to iterate designs and run target-tracking field tests.

Lead RF/analog/mixed-signal chip tapeouts from design through validation, integrate analog IPs into SoCs, prototype high-speed systems, mentor the team, validate silicon with test automation, and contribute to PCB design and firmware bring-up for wearable devices.

Perform RTL integration of IPs and subsystems into top-level SoCs, develop RTL wrappers, interconnect, clock/reset infrastructures; run lint/CDC/early synthesis checks; debug simulation and synthesis issues; automate and maintain integration flows with Python/Perl/Tcl; collaborate with design, verification, and physical design teams and contribute to design reviews and documentation.

Build production-quality, pixel-accurate UI components and interactions in React Native; prototype in Figma with designers; own the design system and component library; improve performance, animations, and cross-platform UI architecture; define design-to-dev tooling and collaborate across design and engineering.

Lead RTL Design Engineer for wireless baseband architecture, overseeing design teams, implementing RTL designs, and ensuring adherence to methodologies.

Join a startup as a Physical Design Engineer, focusing on RTL-to-GDSII implementation, performance optimization, and AI-driven automation.

Design and take digital, analog, and mixed-signal PCBs from architecture through layout, fabrication, bring-up, testing, and production. Address signal/power integrity, grounding, thermal, and EMI/EMC. Define hardware-firmware interfaces, debug and characterize boards, develop test fixtures, and manage BOMs, documentation, and vendor assembly.

The ASIC Design Engineer will develop SoCs, micro-architecture design, RTL coding, optimization, and collaborate with multiple teams for ASIC development.

Lead mechanical design from concept to production for AMR/AGV systems: create 3D models and drawings, perform tolerance analysis, DFMEA, prototyping, testing, validation, manufacturability optimization, and cross-functional collaboration to support product launches and continuous improvement.

The role involves leading a team of Physical Design engineers in delivering high-performance silicon products while ensuring adherence to timing, power, and area requirements. Responsibilities include technical leadership, hands-on ownership of critical blocks, automation development, and stakeholder management to meet project milestones.

Design, develop and integrate building management and controls for modular datacenter MEP systems. Own control architecture, PLC/HMI/SCADA programming, protocols, vendor review, FAT/SAT commissioning, troubleshooting, and mentor junior controls engineers while aligning with cybersecurity and IT requirements.

Perform IC physical design from netlist to GDS: floorplan, implementation, timing closure, STA, ECOs, verification (FV/CLP/PV). Handle medium/complex blocks (~400K–800K instances), debug congestion, high-utilization and multi-voltage designs. Use EDA tools (ICC/ICC2, Synopsys STARXT/PTSI, Olympus/Calibre, Rehawk). Perl/Tcl scripting, IR-drop analysis and low-power design are desirable.

Perform full-chip functional verification including RTL-to-RTL and RTL-to-netlist FV, execute Conformal ECO flows, and debug non-equivalence issues for Qualcomm chip designs. Collaborate on verification tasks onsite in Bangalore.

Design and develop mechanical systems for aerospace applications, focusing on ruggedness and lightweight mechanisms, while collaborating with diverse teams.

The Lead RF Hardware Design Engineer will lead the design and development of RF hardware for satellite communication systems, guiding a team through complex design challenges.

Develop and execute block- and system-level verification plans for complex SoC and silicon designs using PCIe and CXL protocols. Create UVM test sequences, assertions, cover properties, randomized constraints, and VIP abstraction layers. Analyze coverage and system-level performance, debug failures with RTL designers, and verify Physical, Link, and Transaction Layers across PCIe/CXL endpoint and root-complex implementations.

The Microarchitect and RTL Design Engineer will design microarchitectures, ensure optimal performance in RTL coding, and collaborate with software and verification teams to meet project requirements.

Designs and reviews electrical systems including switchgear, transformers, MCCs, cables, lighting, grounding, and lightning protection. Prepares load, cable, interconnection, and motor-starting schedules, along with electrical layouts and single-line diagrams. Supports electrical installation, testing, commissioning, site execution, safety, quality, and schedule compliance. Coordinates contractors, subcontractors, clients, site teams, and other departments, and travels to client offices or construction sites to resolve technical queries.

Designs electrical and instrumentation systems for process industries, including SLDs, cable trays, transformer and cable sizing, PCC/MCC schemes, lighting, and lightning protection. Selects PLC/DCS automation systems and electrical equipment, prepares GA and layout drawings in AutoCAD, reviews vendor drawings and documents, conducts vendor inspections, and visits customer sites for meetings and troubleshooting.

Lead full-chip or large-block physical implementation from netlist to GDSII. Drive floorplanning, placement, CTS, routing, STA timing closure, DRC/LVS/EM/IR signoff, ECOs, hard-macro integration, PPA optimization, and automation scripting while collaborating with RTL, architecture, verification, and foundry teams.

Design and integrate RF systems for ground and space applications: define system requirements and architecture, select components, perform RF simulations, carry out component characterization, integrate and validate hardware using RF test equipment, and collaborate with cross-functional teams to meet system specifications.

Own end-to-end UI/UX and frontend implementation: design user flows, craft high-fidelity prototypes, build responsive React+TypeScript interfaces, implement scalable component architecture, integrate with REST/GraphQL APIs, optimize performance, and collaborate with backend and product teams in a regulated life-sciences context.