Top Design Engineer Jobs in Bengaluru

The Lead Design Engineer will perform pre and post silicon Physical Layer Electrical Validation on High Speed SERDES IP. Responsibilities include designing hardware/software infrastructure, implementing rigorous test suites, debugging silicon issues, and generating test reports.

As a Principal Design Engineer at Cadence, you will lead the design of Analog Mixed Signal (AMS) for High-speed Memory PHYs. You will oversee subsystems, mentor team members, participate in technical discussions, and ensure quality and efficiency in AMS design.

Work with the Cadence global IC design team to develop semiconductor IP for top electronic product companies, ensuring continuous quality improvement and adherence to quality procedures.

Lead Design Engineer responsible for creating and maintaining functional verification environments, defining verification strategies, and collaborating with cross-functional teams. Requires expertise in Verilog, SystemVerilog, UVM methodology, RTL, and various verification domain skills. Desirable skills include power-aware RTL, formal verification, gate-level simulations, and exposure to automotive IP verification.

Cadence is looking for a passionate Layout Design professional with 2-14 years of experience in Analog Layout and SerDes IP. The role involves working on cutting edge FinFET technologies and collaborating with Tier-1 customers. Responsibilities include hands-on layout experience in various analog IPs, knowledge of layout effects on circuits, understanding of DSM technology, and communication skills. Scripting and automation experience is a plus.

Looking for a Senior Principal RTL Design Engineer with 12+ years of ASIC design experience. Proficiency in Verilog coding, RTL design, and various interface protocols. Must have knowledge of RTL checks and synthesis flow.

Join a growing team at Cadence as a Sr Principal Design Engineer, responsible for leading the Design for Test activities for next-gen SoCs. Define DFT architecture, implement verification logic, collaborate with teams, and work on silicon bring up. Ideal candidate has 8-15+ years of experience with key DFT concepts and working knowledge of Verilog coding

Principal DFT Design Engineer responsible for mentoring junior engineers, driving innovation/automation, working with cross-functional teams, and leading DFT methodology advancements to improve quality and reliability.

Design Engineer I with 1+ years of experience in analog/mixed-signal layout design of deep sub-micron CMOS circuits. Responsibilities include custom and standard cell based floor-planning, achieving tight matching, low noise, and low power consumption in layouts, managing various layout parameters, collaborating with circuit designers, and interpreting reports. Knowledge of CADENCE layout tools and scripting skills in PERL or SKILL are a plus.

Design Engineer II at Cadence with 2-4 years (with Btech) or 1-2 years (with Mtech) of experience in Post-Silicon Physical Layer Electrical Validation. Responsibilities include deep physical layer electrical validation on high-speed SERDES protocols, using lab equipment, managing small teams, leading post-silicon validation efforts, FPGA design, PCB schematic and layout design, and more.

The IC Design Engineer will work on SOC physical design activities including floor-planning, partitioning, placement, and physical verification. The role involves achieving timing and area metrics, doing timing analysis, power optimization, and implementing ECOs. The candidate should possess strong problem-solving skills, experience with verification tools, and effective communication skills.

The Backend Physical Design Engineer will oversee and optimize the physical design process, focusing on SoC integration and layout activities. Responsibilities include implementing timing and functional ECO, utilizing EDA tools, and developing automation flows to enhance design quality and turnaround time.

The Senior Memory Design Engineer will lead the design and development of SRAM memory compilers and perform circuit design/simulation, statistical analysis, and timing analysis. Responsibilities include design tuning and performance sign-off to meet yield targets, as well as conducting signal and power integrity analysis.

This role involves the physical design of 3nm/5nm Multi-GHz ASIC products, including creating floorplans, power plans, CTS, and routing. The engineer will use EDA tools, write TCL scripts for P&R optimizations, and work on ensuring timing closure while collaborating with cross-functional teams.

The Senior IC Design Engineer will develop and verify RTL designs for digital and memory subsystems, focusing on DFT. Responsibilities include insertion and verification signoff for memory subsystems, conducting formal and cross-clock domain verifications, and independently creating verification suites using OVM or UVM methodologies.

The Senior Design Engineer will work primarily on RTL development and verification for digital memory subsystems. Responsibilities include DFT insertion, static timing analysis, and creating verification suites using OVM and UVM methodologies while collaborating with cross-functional teams to ensure timing closure.

The Backend Physical Design Engineer will lead Broadcom's design methodology for silicon integration, focusing on physical design activities at the block and SoC level. Responsibilities include layout, timing and functional ECOs, automation flows, and ensuring timely and quality execution of tasks using EDA tools.