Top Design Engineer Jobs in Bengaluru, KA

Develop highly optimized software for automotive applications on Renesas R-Car SoC devices. Collaborate with sales and engineers to create winning reference software. Conduct benchmarks and provide customer support.

Join Renesas as a Sr Principal Analog Design Engineer in the Power Design Team, developing next-generation IC products for consumer, industrial, and automotive power products. Responsibilities include block level design, interface with internal teams, drive specifications, simulation, and test support. Requires 20+ years of experience in design engineering, with a track record in managing global teams and successful product development.

Join the Power Design Team at Renesas Electronics America working on next-generation IC products for consumer, industrial, and automotive power products. Responsibilities include analog and power design, block-level design, interface with various teams, simulation, and test support. Requires BSEE (MSEE pref.) with 20+ years experience in Analog design engineering role.

Design optimized digital blocks meeting functional, cost, and low power constraints, develop TCL scripts and design constraints, support DFT strategy and implementation, verification planning, develop test vectors, and produce high-quality documentation for own blocks.

Senior Physical Design Engineer with hands-on experience in synthesis, timing closure, formal verification, and full chip ownership. Must have expertise in Cadence and/or Synopsys tools, System Verilog/Verilog, DFT, and scripting in Python or Perl. Knowledge of DFT test coverage, ECO methodologies, and working with IP vendors is required.

Seeking a Principal Physical Design Engineer with ≥10 years of experience in supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. Must have hands-on knowledge of synthesis, place and route, timing, extraction, and other backend tools for technologies 16nm or less. Experience with Cadence and/or Synopsys tools, System Verilog/Verilog, DFT tools, and IP vendors required. Salary based on experience level.

Join a diverse group responsible for high-speed digital and analog circuit designs. Execute IC layout for cutting-edge circuits in advanced CMOS process nodes. Deliver layouts for digital cum analog IPs and follow best practices. Requires 2+ years of experience in high-performance analog layout and knowledge of Cadence tools.

As a UX Design Engineer at Hewlett Packard Enterprise's Aruba, you will gather and evaluate UX requirements, depict design concepts, and create high fidelity mocks for B2B products. The role requires practical knowledge of UX theory, proficiency in Figma, and strong communication skills. A Bachelor's degree and 7+ years of UX design experience, preferably in the networking industry, are required.

Design Engineer I with 1+ years of experience in analog/mixed-signal layout design of deep sub-micron CMOS circuits. Responsibilities include custom and standard cell based floor-planning, achieving tight matching, low noise, and low power consumption in layouts, managing various layout parameters, collaborating with circuit designers, and interpreting reports. Knowledge of CADENCE layout tools and scripting skills in PERL or SKILL are a plus.

Infinera is seeking an experienced Optical Engineer to join their Hardware design group in Bengaluru, India. This role involves hands-on work with system-level optical communication hardware and components. The Optical Engineer will play a key role in designing and characterizing high-complexity DWDM equipment for Metro, Long-Haul, Ultra-Long-Haul applications, and Coherent Transceivers.

As a Senior Manager ASIC Design Engineer at Infinera, you will be responsible for managing the design execution of ASIC and FPGA projects. You will work closely with various teams to estimate scope of work, monitor project execution, and provide leadership to a team of Engineers.

Design Engineer- Data Solutions position for an innovative organization specializing in electrical solutions. Responsibilities include applying technological expertise to projects, analyzing products, collaborating with cross-functional teams, and translating customer needs into product specifications. Requires Bachelor's degree in Mechanical Engineering, 3+ years of experience, and knowledge in hydronic systems, electrical schematics, and heat transfer. Experience with design tools like DFMEA and SolidWorks is essential.

Join a growing team at Cadence as a Sr Principal Design Engineer, responsible for leading the Design for Test activities for next-gen SoCs. Define DFT architecture, implement verification logic, collaborate with teams, and work on silicon bring up. Ideal candidate has 8-15+ years of experience with key DFT concepts and working knowledge of Verilog coding

Looking for a Senior Principal RTL Design Engineer with 12+ years of ASIC design experience. Proficiency in Verilog coding, RTL design, and various interface protocols. Must have knowledge of RTL checks and synthesis flow.

Cadence is looking for a passionate Layout Design professional with 2-14 years of experience in Analog Layout and SerDes IP. The role involves working on cutting edge FinFET technologies and collaborating with Tier-1 customers. Responsibilities include hands-on layout experience in various analog IPs, knowledge of layout effects on circuits, understanding of DSM technology, and communication skills. Scripting and automation experience is a plus.

Principal DFT Design Engineer responsible for mentoring junior engineers, driving innovation/automation, working with cross-functional teams, and leading DFT methodology advancements to improve quality and reliability.

Design Engineer II at Cadence with 2-4 years (with Btech) or 1-2 years (with Mtech) of experience in Post-Silicon Physical Layer Electrical Validation. Responsibilities include deep physical layer electrical validation on high-speed SERDES protocols, using lab equipment, managing small teams, leading post-silicon validation efforts, FPGA design, PCB schematic and layout design, and more.