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Top Design Engineer Jobs in Bengaluru

24 Days Ago
Bengaluru, KA
100 Employees
Senior level
100 Employees
Senior level
Semiconductor
The Physical Design Engineer Lead will oversee the physical design implementation of low-power, high-performance SoCs, including logic synthesis, floor planning, power planning, and timing closure. Responsibilities include resolving design issues, automating processes using EDA tools, and interfacing with RTL and cross-functional teams for modifications.
24 Days Ago
Bengaluru, KA
100 Employees
Senior level
100 Employees
Senior level
Semiconductor
The Senior Physical Design Engineer is responsible for the physical design implementation of low-power and high-performance SoC, collaborating with RTL and system design teams. Duties include logic synthesis, floor planning, power planning, place and route, and static timing closure, while also automating processes using EDA tools to enhance quality and throughput.
24 Days Ago
Bengaluru, KA
148 Employees
Senior level
148 Employees
Senior level
Big Data • Information Technology
The Senior Physical Design Engineer at Astera Labs will focus on developing complex SoC/silicon products for Server, Storage, and Networking applications, overseeing full chip or block level ownership from architecture to GDSII. This role requires expertise in physical design tools, synthesis, timing closure, and scripting, aimed at driving multiple complex designs to production.
24 Days Ago
Bengaluru, KA
148 Employees
Expert/Leader
148 Employees
Expert/Leader
Big Data • Information Technology
The Principal Physical Design Engineer at Astera Labs will lead the development of complex SoC/silicon products for Server, Storage, and Networking applications, overseeing full chip or block ownership from architecture to GDSII, utilizing advanced physical design methodologies.
24 Days Ago
Bengaluru, KA
12,676 Employees
Mid level
12,676 Employees
Mid level
Semiconductor
As a Memory Design Engineer at GlobalFoundries, you will design and simulate custom memory blocks like SRAM and ROM while collaborating with various teams for verification and testing. Your responsibilities include circuit design, functional simulations, and supporting silicon bring-up, all aimed at achieving top quality in memory IP releases.
24 Days Ago
Bengaluru, KA
Hybrid
943 Employees
Senior level
943 Employees
Senior level
Energy
The Senior Mechanical Design Engineer will be responsible for the structural design of enclosures, performing design verification, and ensuring compliance with international standards. Responsibilities include leveraging CAD tools for design, performing analyses, and collaborating with cross-functional teams. The ideal candidate will possess strong engineering skills and a broad mechanical engineering background with experience in cooling systems and enclosure structures.
24 Days Ago
Bengaluru, KA
Hybrid
943 Employees
Mid level
943 Employees
Mid level
Energy
Design and develop mechanical systems for Fluence's energy storage products, focusing on CAD modeling and engineering solutions. Responsibilities include creating 3D models, generating technical specifications, ensuring design compliance with international standards, and collaborating with cross-functional teams.
2 Days Ago
Bengaluru, KA
636 Employees
Senior level
636 Employees
Senior level
Semiconductor
The Senior Engineer I will drive the backend process through the implementation flow, including tasks such as floor-planning, low-power design, place & route, and static timing verification. They will also perform physical verification and ensure power integrity in IC design.
2 Days Ago
Bengaluru, KA
636 Employees
Senior level
636 Employees
Senior level
Semiconductor
You will manage the design/RTL team, provide technical support to customers, propose architecture based on requirements, and ensure project goals are met through effective team collaboration and methodology improvements.
3 Days Ago
Bengaluru, KA
389 Employees
Entry level
389 Employees
Entry level
Hardware • Manufacturing
The Staff Design Verification Engineer will define verification plans, develop DV environments independently, and execute test plans to ensure quality and reliability of IP solutions. Expertise in System Verilog and UVM methodologies is essential, along with a strong focus on functional verification at the RTL level.
8 Days Ago
Bengaluru, KA
7,216 Employees
Senior level
7,216 Employees
Senior level
Digital Media
The Design System Lead Engineer will manage a skilled team to enhance the design system, ensuring visual identity consistency and improving user experiences across brands. Responsibilities include mentoring the team, collaborating to align goals, overseeing design tokens, leading feature development, maintaining documentation, and ensuring quality assurance.
5 Days Ago
Bengaluru, KA
6,975 Employees
Junior
6,975 Employees
Junior
Energy
The Junior Engineer Design is responsible for independently performing structural analysis and design work, and checking drawings provided by draftsmen. The role requires a proactive learner with the ability to work with minimal support.
6 Days Ago
Bengaluru, KA
636 Employees
Senior level
636 Employees
Senior level
Semiconductor
As a Principal Engineer - RTL Design at Alphawave Semi, you'll lead a team in micro-architecture development, oversee pre-sales architectural proposals, manage design team deliverables, and collaborate with customers and IP vendors to meet project goals while improving methodology for high reuse.
6 Days Ago
Bengaluru, KA
173 Employees
Senior level
173 Employees
Senior level
Automotive
The role involves verifying DSP designs for SoCs and FPGAs, defining and developing verification environments using SystemVerilog and UVM, building self-checking environments with C/C++, executing verification plans, and collaborating with cross-functional teams to ensure high-quality delivery.
7 Days Ago
Bengaluru, KA
80,000 Employees
Senior level
80,000 Employees
Senior level
Healthtech • Telehealth
The Design Quality Engineer will ensure software quality through documentation, compliance with standards, and problem-solving within software quality management in the Medtech industry. Key responsibilities include assessing quality plans, conducting root cause analyses, and collaborating with technology teams for certification and inspections.
7 Days Ago
Bengaluru, KA
552 Employees
Senior level
552 Employees
Senior level
Software
The Senior Engineer in Design Verification Power Management at SiFive will lead efforts related to low power management strategies and drive multiple projects. Responsibilities include power simulation, script writing in various programming languages, and assessing power impact across different design levels.
7 Days Ago
Bengaluru, KA
12,676 Employees
Senior level
12,676 Employees
Senior level
Semiconductor
The Senior Staff Engineer will lead the development of innovative semiconductor design automation workflows focused on integrating automation and AI techniques. Responsibilities include mentoring, enhancing design efficiency, deploying new design flows, and collaborating with cross-functional teams.
7 Days Ago
Bengaluru, KA
38,985 Employees
Senior level
38,985 Employees
Senior level
Semiconductor
The R&D Engineer IC Design designs and develops integrated circuits, oversees ASIC development, and performs architecture and system simulations. The role involves evaluating processes, conducting experimental tests, and leading projects while mentoring junior team members.
8 Days Ago
Bengaluru, KA
485 Employees
Senior level
485 Employees
Senior level
Industrial • Manufacturing
Lead the architectural design and implementation of applications for digital equipment in food & beverage. Responsibilities include designing, developing, and maintaining Linux applications, integrating with system libraries, and mentoring junior developers. Collaborate with cross-functional teams to ensure optimal performance and quality assurance while maintaining technical documentation.
8 Days Ago
Bengaluru, KA
6,500 Employees
Senior level
6,500 Employees
Senior level
Semiconductor
As a Staff Engineer in Physical Design at Marvell, you will lead the physical design and methodology for high-performance processor chips, including synthesis, place and route, and timing analysis. You will collaborate with teams to develop timing and logic modifications, resolve timing issues, and enhance design processes.
8 Days Ago
Bengaluru, KA
6,500 Employees
Senior level
6,500 Employees
Senior level
Semiconductor
As a Senior Staff Engineer in Physical Design at Marvell, you will manage physical design and methodologies for next-gen processor chips using advanced EDA tools. Your responsibilities include synthesis, place and route, timing analysis, and collaboration with global teams to resolve timing issues while mentoring juniors in a diverse engineering team. You will engage in complex engineering challenges in a highly collaborative environment.
8 Days Ago
Bengaluru, KA
6,500 Employees
Senior level
6,500 Employees
Senior level
Semiconductor
The Staff Engineer will work on physical design and methodology for high-performance processor chips. Responsibilities include maintaining and enhancing Place and Route Flow, performing synthesis, place and route, timing analysis, and collaborating with the RTL design team to address timing issues. The role involves debugging block-level timing issues in a collaborative environment.
8 Days Ago
Bengaluru, KA
6,500 Employees
Senior level
6,500 Employees
Senior level
Semiconductor
In this role, you will design and implement physical design methodologies for high-performance processor chips within a global team. Responsibilities include managing the Place and Route flow using EDA tools, performing synthesis and timing analysis, and collaborating with design teams to resolve timing issues.
8 Days Ago
Bengaluru, KA
6,500 Employees
Senior level
6,500 Employees
Senior level
Semiconductor
The Staff Engineer in Physical Design at Marvell will work on the physical design and methodology for processor chips, utilizing EDA tools for synthesis, place and route, and timing analysis. Responsibilities include developing and implementing timing and logic modifications and resolving timing issues in collaboration with the RTL team.
8 Days Ago
Bengaluru, KA
6,500 Employees
Senior level
6,500 Employees
Senior level
Semiconductor
As a Senior Staff Engineer at Marvell, you will focus on physical design and methodology for high-performance processor chips. You will maintain and enhance Place and Route flows using EDA tools, perform synthesis, place and route, and timing analysis, and collaborate with RTL design teams on timing and logic ECOs. Involvement with global teams for debugging block-level timing issues is also key.
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